The phase locked loop (PLL) and clock and data recovery (CDR) circuit are two major blocks of any digital communication system. The design of these blocks has a direct impact on the performance of the communication system. Several ways to define the figures of merit for these blocks may be translated into certain requirements in terms of the phase margin and the bandwidth of the loop. Because system requirements may include requirements on phase margin and bandwidth, there is a need for a system and a method for designing a PLL or CDR circuit for a given bandwidth and phase margin requirement.